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Date of publication: 19-04-2023 Update date: 10-04-2026 🕒 11 min read
The world of today is dominated by digital systems – computers, smartphones, but also smart fridges or home automation systems that make our lives easier. In this context, advanced industrial systems are just too obvious to mention. Efficient operation of all such devices largely depends on smartly designed electronic systems equipped with processors, but also storage and data processing circuits. Each of these can be treated as a separate electronic component, but in reality these chips are made up of a huge number of smaller elements referred to as logic gates. Logic gates are in turn made up of even smaller components, i.e. transistors. However, in this article, we will not describe this design level, as we will focus solely on logic gates.
How do computers really work? Every task performed by a central processing unit (CPU), whether it is surfing the Internet or using software, ultimately boils down to mathematical calculations and data transfer.
However, computers make calculations in a slightly different way than you might think. In our lives, we are used to decimal arithmetic, i.e. the arithmetic in which ten digits, from 0 to 9, are used. With these, we can create larger numbers. The computer’s mode of operation is, however, slightly different, as it is based on the binary system. It means that it uses only two digits, i.e. 0 and 1, to create other numbers. In digital systems, zeros and ones are called logic states (0 – low state, 1 – high state), and are closely related to voltage levels. Simply speaking, zero means “no voltage” and one means “voltage is present”.
Both decimal and binary arithmetic systems are governed by certain laws. In this case, we use the Boolean algebra, from which certain logic functions are derived. The logic gates mentioned above are based on them, i.e. each gate fulfils one of the basic logic functions. By combining them to create larger structures, we can design even very complex systems, e.g. processors.
Initially, logic gates were designed as individual integrated circuits (ICs), possibly integrating several such structures. Back then, engineers who wanted to build a larger device had to design sizeable systems comprising numerous individual integrated circuits. The first computers, whose components had to be distributed across several rooms, are a good example of this. Initially, they were designed using systems based on the TTL (transistor-transistor logic) technology, i.e. systems accommodating bipolar transistors. Thanks to introducing the TTL chips, the very first logic standard was designed, in which systems were supplied with 5 V voltage, and the high- and low-state voltage ranges were 2 V–5 V and 0.4 V–0.8 V, respectively. Later, systems based on field-effect transistors (FET) were designed (designated as Complementary Metal-Oxide-Semiconductor, i.e. CMOS, systems). There are several differences between TTL and CMOS systems, the most important of which include power supply voltage and power consumption. As compared to their predecessors, CMOS systems can be powered with much higher voltages (up to about 15 V), and they also consume much less current, which is particularly useful when it comes to designing battery-powered systems.
The technological development has resulted in rapid miniaturisation. Obviously, the same applies to logic gates (even if some of them are still made as individual circuits), which have become an inseparable part of the silicon cores of integrated circuits. Recently, single logic gates housed in small SMD enclosures have also gained popularity. They are a very convenient solution, given that electronic equipment manufacturers constantly strive to reduce costs.
Note also that logic gates are asynchronous systems. This feature distinguishes them from most of the currently used systems which need a clock signal to function as required, referred to as synchronous systems. In logic gates, the output signal responds almost instantaneously to input pulse changes. Here, the propagation times, i.e. nanoseconds during which the silicon structure responds to changes in voltage, are the only limitation.
As mentioned above, each gate fulfils a specified logic function. Below, various types of logic gates are described, based on selected examples.
The NOT gate is one of the simplest designs. It comes with one input and one output. This gate fulfils the negation function, i.e. reversing the state from the input and passing it to the output. When a high state is applied at the input, the output state becomes low. Similarly, while applying a low state at the input, the logical 1 is present at the output. The operations of logic gates are usually described in “truth tables”.
| A | Y |
|---|---|
| A | Y |
| 1 | 0 |
| 0 | 1 |
Such tables simply present the gate operation principles in a graphic form. On the left-hand side, the column corresponding to input A contains all the states that this input can accept, i.e. 1 and 0. On the other side, there are those that will then appear at the gate output marked as Y. In addition, a NOT gate can be described by the following equation: , i.e. the negated signal A is obtained at input Y. The negative state is marked with a horizontal line placed over a letter.
The symbol of the NOT gate is a small triangle, with the input and the output on its sides. At the output, there is a small circle.
The AND gate is a two-input design in which the logical 1 appears at the output only when the high state is applied to both inputs. In other words, AND functions as a product (AND operation) described as Y = AB. Note that the AND gate may have more inputs, but its principle of operation remains unchanged in those situations, too.
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The AND gate symbol resembles a combination of half a square and a circle with the inputs located on the left and one output on the right.
Another basic logic gate is the NAND gate, i.e. an inversed AND gate. At its output, a high state appears in all but one case, i.e. except for when a high state is applied to all inputs. One may visualise the NAND gate as the AND gate with an additional (one or more) NOT gate placed at its output. Note that, just as in the case of the AND gate, the number of inputs is almost unlimited here.
| A | B | Y |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The NAND gate is sometimes described with a logic function expressed by the following equation: Y=\bar{AB}. The NAND symbol is almost identical to the AND gate symbol, but the circle is placed at the output.
Another basic logic gate design it the logical sum (logical disjunction) function. It is referred to as the OR gate. As its name suggests, this gate adds signals from possibly numerous inputs. In other words, there is the logical 1 at the output when any of the inputs accepts that particular state. On the other hand, if several or even all of the inputs show the high state, the output also accepts it.
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
The logic function describing the OR gate is Y = A+B, and its symbol is different from the above-mentioned gate symbols, i.e. is similar to an “arrow-head”.
Just as the NAND gate is the inverse of AND, the NOR gate is an inverse of the OR gate. There are other similarities, too, as the NOR gate can also be visualised as the OR gate, with one or several NOT gates placed at the output to negate the states of possibly numerous inputs (as in the case of previously mentioned designs). Its principle of operation is quite simple, as we obtain a high state at the output only if the logical zero appears at all inputs. It is demonstrated by the following function:
| A | B | Y |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
The NOR gate symbol shape resembles an arrow-head (similarly to OR) with a circle placed at the output. Similarly, the inputs are placed on the left and the outputs on the right.
A gate designated as XOR is also one of classic logic structures. Its operation is quite interesting, because it only switches an output to the high state when the inputs are different from one another. In other words, this happens when 1 is applied to one of the inputs and 0 to the other one. If all inputs assume the same state, the logical zero appears at the gate output. This logic function is described with the following equation: , and referred to as the “logical disjunction” or “modulo 2 sum”.
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The graphical representation of the XOR gate is shaped as an arrow-head (similar to OR and NOR gates), however, with an additional line placed in parallel to its left side. Inputs and outputs are typically located on the left and right side.
The XOR gate also comes with its inverse structure referred to as XNOR. As in other “inverse” structures, its operation consists in negating the base gate. In this case, in order to obtain a high state at the output, the same state must be applied to all inputs, regardless of the fact whether it is a logical 1 or zero.
| A | B | Y |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The XNOR gate operation is described with the following formula: , and its symbol is almost the same as the XOR symbol, but an additional small circle is placed at the output.
Buffers and three-stage buffers are quite interesting designs that can be included in the logic gate group. Judging by their graphic symbol only, they can be associated with a NOT gate, however, without the circle located at the output. So is a buffer the inverse of a NOT gate? Well, it is, but why use the inverse of negation, which basically implies the transfer of the input state to the output, if such a gate does not perform any logical function? The answer to this question lies in the current efficiency. The output of any logic gate has its specific capacity, i.e. we can connect to it only a certain number of other gate inputs or LEDs (for example). If the capacity threshold is exceeded, the gate becomes irreversibly damaged. In such a case, a buffer whose output current capacity is much higher should be used. It does not change the signal state, but makes it possible to connect a larger number of receivers.
Another symbol presented in the graphic is a three-stage buffer. It does not change the signal state either, but comes with an additional input marked as “S”. It “disconnects” the output or, professionally speaking, puts it into a high-impedance state denoted by the letter Z. In this state (also called the undefined state), we cannot tell what signal is present at the gate output; it can be imagined as a wire hanging in the air, to which nothing is connected.
| A | S | Y |
| 0 | 0 | Z |
| 0 | 1 | 0 |
| 1 | 0 | Z |
| 1 | 1 | 1 |
If a three-stage buffer is activated with a high state at input S, it is only in this case that the state from the input gets transferred to the output; otherwise, the output is put into a high-impedance state. Such designs are used to enhance current efficiency performance, but also when a circuit must be disconnected from the rest of the system. Moreover, three-stage buffers were used in large digital structures where data was transmitted via buses. It facilitated disconnecting a module from a bus, so that the other parts of the system could transfer information between one another effortlessly.
While discussing logic gates, one must also mention the methods and principles of connecting them. To put it simple, never connect gate outputs! It is a generally accepted rule that must be complied with. For example, two AND gates generate a signal at the output to activate a single LED – in such a case, the two outputs of the gate and LED anode cannot be connected. “Why not?” is the obvious question... However, the answer is just as obvious – imagine what would happen if the 1 appeared at the output of one of the gates, while the output of the other one was in the low state. Looking from the perspective of the first gate, the output of the second gate is simply “ground”, so the current will not flow through the LED, but through the output of the second gate, causing its irreparable damage.
This problem can be solved by using the third gate whose inputs are connected with the AND gates’ outputs. In this case, if each signal is to activate the LED, the OR gate must be used. Then, no matter at which AND output gate the high state is present, the OR gate will activate its output, thereby allowing current to flow through the LED.
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